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Charge Pump Regulator for Color TFT Panel ADM8832
FEATURES
3 output voltages (+5.1 V, +15.3 V, -10.2 V) from one 3 V input supply Power efficiency optimized for use with TFT in mobile phones Low quiescent current Low shutdown current (<1 A) Fast transient response Shutdown function Power saving during blanking period Option to use external ldo
FUNCTIONAL BLOCK DIAGRAM
VCC C5 2.2F C1+ C1- VOUT CLKIN SCAN/ BLANK LDO_ON/ OFF OSCILLATOR LDO VOLTAGE REGULATOR CONTROL LOGIC DOUBLE LDO IN C6 2.2F +5VOUT +5VIN C2+ C2- C2 1F C3 1F +15.3V C8 1F C1 2.2F
ADM8832
VOLTAGE DOUBLER
+5.1V C7 2.2F
APPLICATIONS
Handheld instruments TFT LCD panels Cellular phones
SHDN
TIMING GENERATOR VOLTAGE TRIPLER
TRIPLE
C3+ C3-
+15VOUT C4+ C4- C4 1F
VOLTAGE SHUTDOWN DISCHARGE INVERTER CONTROL
GND
-10.2V C9 1F
Figure 1.
GENERAL DESCRIPTION
The ADM8832 is a charge pump regulator used for color thin film transistor (TFT) liquid crystal displays (LCD). Using charge pump technology, the device can be used to generate three output voltages (+5.1 V 2%, +15.3 V, -10.2 V) from a single 3 V input supply. These outputs are then used to provide supplies for the LCD controller (+5.1 V) and the gate drives for the transistors in the panel (+15.3 V and -10.2 V). Only a few external capacitors are needed for the charge pumps. An efficient low dropout voltage regulator also ensures that the power efficiency is high and provides a low ripple 5.1 V output. This LDO can be shut down and an external LDO used to regulate the 5 V doubler output and drive the input to the charge pump section, which generates the +15.3 V and -10.2 V outputs if so required by the user. The ADM8832 has an internal 100 kHz oscillator for use in scanning mode, but the part must be clocked by an external clock source in blanking (low current) mode. The internal oscillator is used to clock the charge pumps during scanning mode where the current is highest. During blanking periods, the ADM8832 switches to an external, lower frequency clock. This allows the user to vary the frequency and maximize power efficiency during blanking periods. The tolerances on the output voltages are seamlessly maintained when switching from scanning mode to blanking mode or vice versa. The ADM8832 power saving features include low power shutdown and reduced quiescent current consumption during the blanking periods. The 5.1 V output consumes the most power, so power efficiency is also maximized on this output with an oscillator enabling scheme (Green IdleTM). This effectively senses the load current that is flowing and turns on the charge pump only when charge needs to be delivered to the 5 V pump doubler output. The ADM8832 is fabricated using CMOS technology for minimal power consumption. The part is packaged in a 20-lead LFCSP (lead frame chip scale package).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
03759-A-001
-10VOUT
ADM8832 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Scanning and Blanking.............................................................. 10 Power Sequencing ...................................................................... 10 Transient Response .................................................................... 10 External Clock ............................................................................ 10 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11
REVISION HISTORY
4/04--Changed from Rev. 0 to Rev. A Changes to Outline Dimensions................................................... 11 Updated Ordering Guide............................................................... 11 7/03--Revision 0: Initial Version
Rev. A | Page 2 of 12
ADM8832 SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted; C1, C5, C6, C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode. Table 1.
Parameter INPUT VOLTAGE, VCC SUPPLY CURRENT, ICC Min 2.6 Typ 150 70 Max 3.6 400 140 1 5.2 5 8 200 Unit V A A A V mA mA A % % mV p-p s V A A mV p-p V A A mV p-p % % kHz Test Conditions Unloaded, Scanning Period Unloaded, Blanking Period Shutdown Mode, TA = 25C IL = 10 A to 8 mA Scanning Period Scanning Period, VCC > 2.7 V Blanking Period VCC = 3 V, IL = 5 mA (Scanning) VCC = 3 V, IL = 200 A (Blanking) 8 mA Load IL Stepped from 10 A to 8 mA IL = 1 A to 100 A Scanning Period Blanking Period IL = 100 A IL = -1 A to -100 A Scanning Period Blanking Period IL = -100 A Relative to 5.1 V Output, IL = 100 A (Scanning) Relative to 5.1 V Output, IL = 10 A (Blanking) Scanning Period
+5.1 V OUTPUT Output Voltage Output Current
5.0
Power Efficiency Output Ripple Transient Response +15.3 V OUTPUT Output Voltage Output Current Output Ripple -10.2 V OUTPUT Output Voltage Output Current Output Ripple POWER EFFICIENCY (+15.3 V and -10.2 V Outputs) CHARGE PUMP FREQUENCY CONTROL PINS SHDN Input Voltage, VSHDN Digital Input Current Digital Input Capacitance1 SCAN/BLANK Input Voltage 0.7 VCC Digital Input Current Digital Input Capacitance1 LDO_ON/OFF Input Voltage 0.7 VCC Digital Input Current Digital Input Capacitance1
Footnotes after table.
5.1 4 5 50 80 70 10 5 15.3 50 1 50 -10.2 -50 -1 50 90 80 100
14.4
15.6 100 10
-10.4 -100 -10
-9.6
60
140
0.3 VCC 0.7 VCC 1 10 0.3 VCC 1 10 0.3 VCC 1 10
V V A pF V V A pF V V A pF
SHDN Low = Shutdown Mode SHDN High = Normal Mode
Low = BLANK Period High = SCAN Period
Low = External LDO High = Internal LDO
Rev. A | Page 3 of 12
ADM8832
Parameter CLKIN Minimum Frequency Input Voltage VIL VIH Digital Input Current Digital Input Capacitance1 Min 0.9 Typ 1 0.3 VCC 0.7 VCC 1 10 Max Unit kHz V V A pF Test Conditions Duty Cycle = 50%, Rise/Fall Times = 20 ns
1
Guaranteed by design. Not 100% production tested. Specifications are subject to change without notice.
TIMING SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted; C1, C5, C6, C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode. Table 2.
Parameter POWER-UP SEQUENCE +5 V Rise Time, tR5V +15 V Rise Time, tR15V -10 V Fall Time, tF10V Delay between -10 V Fall and +15 V, tDELAY POWER-DOWN SEQUENCE +5 V Fall Time, tF5V +15 V Fall Time, tF15V -10 V Rise Time, tR10V Min Typ 300 8 12 3 75 40 40 Max Unit s ms ms ms ms ms ms Test Conditions/Comments 10% to 90%, Figure 17 10% to 90%, Figure 17 90% to 10%, Figure 17 Figure 17 90% to 10%, Figure 17 90% to 10%, Figure 17 10% to 90%, Figure 17
Rev. A | Page 4 of 12
ADM8832 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter Supply Voltage Input Voltage to Digital Inputs Output Short Circuit Duration to GND Output Voltage +5.1 V Output -10.2 V Output +15.3 V Output Operating Temperature Range Power Dissipation (Derate 33 mW/C above 25C) Storage Temperature Range ESD Ratings -0.3 V to +4.0 V -0.3 V to +4.0 V 10 sec -0.3 V to +6 V -12 V to +0.3 V -0.3 V to +17 V -40C to +85C 3.55 W -65C to +150C Class I
THERMAL CHARACTERISTICS
20-Lead LFCSP: JA = 31C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 12
ADM8832 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
20 C1+ 19 C1- 18 GND 17 -10VOUT 16 C4+
VCC VOUT LDO_IN +5VOUT +5VIN
1 2 3 4 5
PIN 1 INDICATOR
ADM8832
TOP VIEW
15 C4- 14 C2+ 13 C2- 12 C3+ 11 C3-
LDO_ON/OFF 6 SHDN 7 SCAN/BLANK 8 CLKIN 9 +15VOUT 10
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic VCC VOUT LDO_IN +5VOUT +5VIN LDO_ON/OFF Function Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 F decoupling capacitor. Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 F capacitor to ground is required on this pin. Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin. +5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 F capacitor to ground is required on this pin to stabilize the regulator. +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits. Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter circuits of the ADM8832. Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V. Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832. External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current consumption, thus saving power. +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 F capacitor is required on this pin. External capacitor C3 is connected between these pins. A 1 F capacitor is recommended. External capacitor C2 is connected between these pins. A 1 F capacitor is recommended. External capacitor C4 is connected between these pins. A 1 F capacitor is recommended. -10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 F capacitor is required on this pin. Device Ground Pin. External capacitor C1 is connected between these pins. A 2.2 F capacitor is recommended.
7 8
SHDN SCAN/BLANK
9
CLKIN
10 11, 12 13, 14 15, 16 17 18 19, 20
+15VOUT C3-, C3+ C2-, C2+ C4-, C4+ -10VOUT GND C1-, C1+
Rev. A | Page 6 of 12
03759-A-002
ADM8832 TYPICAL PERFORMANCE CHARACTERISTICS
90 70
85 84
LDO POWER EFFICIENCY (%)
LDO POWER EFFICIENCY (%)
60 50 40 30 20
03759-A-003
83 82 81 80 79 78 0 1 2 3 4 5 OUTPUT CURRENT (mA) 6 7 8
03759-A-006 03759-A-008 03759-A-007
10 10
30
50
70 90 110 130 150 OUTPUT CURRENT (A)
170
190
Figure 3. LDO Efficiency in Blanking Mode with VCC = 3 V
5.0752 5.0750 5.0748
Figure 6. LDO Efficiency in Scanning Mode with VCC = 3 V
100
LDO OUTPUT VOLTAGE (V)
5.0746 5.0744 5.0742 5.0740 5.0738 5.0736
03759-A-004
+15V/-10V EFFICIENCY (%)
90
80
70
5.0734 100
60 2 4 6 OUTPUT CURRENT (A) 8 10
1000 BLANKING FREQUENCY (Hz)
10000
Figure 4. LDO Output Voltage (Unloaded) vs. Blanking Mode Frequency
5.104 5.102 5.100 100
Figure 7. +15 V/-10 V Efficiency vs. Output Current in Blanking Mode, VCC = 3 V
90
+15/-10V EFFICIENCY (%)
03759-A-005
80
LDO O/P (V)
5.098 5.096 5.094 5.092 5.090 0 1 2 3 4 ILOAD (mA) 5 6 7 8
70
60
50
40 0 20 40 60 OUTPUT CURRENT (A) 80 100
Figure 5. LDO O/P Voltage vs. Load Current in Scanning Mode, VCC = 3.3 V
Figure 8. +15 V/-10 V Efficiency vs. Output Current in Scanning Mode, VCC = 3 V
Rev. A | Page 7 of 12
ADM8832
5.30 5.25 5.20 DEVICE 1 @ +85C 5.15
TEK STOP: SINGLE SEQ 10.0MS/s [ T
]
LOAD ENABLE 2
DEVICE 1 @ +25C
T
5.0V O/P (V)
5.10
T
5.05 5.00 4.95
03759-A-009
DEVICE 1 @ -40C
1
5V OUTPUT
4.90 2.6
2.7
2.8
2.9
3.0
3.1 3.2 VCC (V)
3.3
3.4
3.5
3.6
CH1 20.0mV
CH2
2.00V
M5.00s
CH2
1.20V
Figure 9. LDO Variation over Supply and Temperature
300
Figure 12. 5 V Output Transient Response for Max load Current
TEK STOP: SINGLE SEQ 10.0MS/s [ T T LOAD DISABLE
]
250
SUPPLY CURRENT (A)
200 ICC (SCAN) 150
2
100 ICC (BLANK) 50
5V OUTPUT 1 T
2.7
2.8
2.9
3.0
3.1 3.2 VCC (V)
3.3
3.4
3.5
3.6
CH1 20.0mV
CH2
2.00V
M5.00s
CH2
1.20V
Figure 10. Supply Current vs. Voltage
TEK STOP: 2.50MS/s [ VOUT T 2 23 ACQS T
Figure 13. 5 V Output Transient Response, Load Disconnected
TEK STOP: SINGLE SEQ 5.00KS/s [ T
]
] +15V OUTPUT
5V OUTPUT RIPPLE 1 T
T 2 T
VCC RIPPLE 3
T
-10V OUTPUT T
03759-A-011 03759-A-014
5VOUT 1 CH1 CH3 5.00V 5.00V CH2 5.00V M10.0ms CH2 1.3V
CH1 20.0mV CH3 50.0mV
CH2 100mV
M20.0s
CH1
-2.8mV
Figure 11. Output Ripple on LDO (5 V Output)
Figure 14. +15 V and -10 V Outputs at Power-Up
Rev. A | Page 8 of 12
03759-A-013
0 2.6
03759-A-010
03759-A-012
ADM8832
TEK STOP: 500S/s [ 5 ACQS T
20.1
]
+15V OUTPUT
20.0
T
DISSIPATED POWER (mW)
19.9 19.8 19.7 19.6 19.5
1
-10V OUTPUT
T T
03759-A-015
5VOUT 2 CH1 CH3 5.00V 5.00V CH2 5.00V M10.0ms CH1 0V
19.4 -40
-20
0
20 40 TEMPERATURE (C)
60
90
Figure 15. +15 V and -10 V Outputs at Power-Down (Unloaded)
Figure 16. Power Dissipation over Temperature, VCC = 3.6 V, Scanning Mode with All O/Ps at Maximum Load
Rev. A | Page 9 of 12
03759-A-016
ADM8832 THEORY OF OPERATION
SCANNING AND BLANKING
A TFT LCD panel is made up of a bank of capacitors, each representing a pixel in the display. These capacitors store different levels of charge, depending on the amount of luminescence required for a given pixel. When a picture is displayed on the panel, a scan of all the pixel capacitors is performed, placing different levels of charge on each in order to create the image. The process of updating the display like this is called scanning. Once scanned, an image is held by pixel capacitance, and the controller and source line drivers can be put into a low power mode. This low power mode is referred to as the blanking mode on the ADM8832. Over a finite period of time, this pixel charge will leak and the capacitors will need to be refreshed in order to maintain the image. The ADM8832 uses scanning and blanking modes, as follows. When the TFT LCD panel is in scanning mode, a logic high on the SCAN/BLANK input places the device in high current power mode, providing extra power (extra current) to the LCD controller and the source line drivers. If the panel continues to be updated (as when a moving picture is being displayed), the ADM8832 can be continually operated in scanning mode. If the same image is kept on the panel, a logic low is applied to the SCAN/BLANK input, and the ADM8832 enters blanking (low current) mode. Depending on how often the image is updated, the ADM8832 can be operated with a variable SCAN/ BLANK duty cycle. This helps to maximize power efficiency and, therefore, extends the battery life.
TRANSIENT RESPONSE
The ADM8832 features extremely fast transient response, making it very suitable for fast image updates on TFT LCD panels. This means that even under changing load conditions there is still very effective regulation of the 5 V output. Figure 12 and Figure 13 show how the 5.1 V output responds when a maximum load is dynamically connected and disconnected. Note that the output settles within 5 s to less than 1% of the output level.
EXTERNAL CLOCK
The ADM8832 has an internal 100 kHz oscillator, but an external clock source can also be used to clock the part. This clock source must be applied to the CLKIN pin. Power is saved during blanking periods by disabling the internal oscillator and by switching to the lower frequency external clock source. To achieve optimum performance of the charge pump circuitry, it is important that the duty cycle of the external clock source is 50% and that the rise and fall times are less than 20 ns.
90%
10%
tR tH
tF tR: RISE TIME tF: FALL TIME tH @ 100% = DUTY CYCLE tT
03759-A-017
POWER SEQUENCING
The gate drive supplies must be sequenced such that the -10 V supply is up before the +15 V supply for the TFT panel to power on correctly. The ADM8832 controls this sequence. When the device is turned on (a logic high on SHDN), the ADM8832 allows the -10 V output to ramp immediately, but holds off the +15 V output. It continues to do this until the negative output reaches -3 V. At this point, the positive output is enabled and allowed to ramp up to +15 V. This sequence is shown in Figure 17.
VCC SHDN
tT
Figure 18. Duty Cycle of External Clock
0.280 0.400
0.100
0.750
0.500
0.050
0.900
1.950
tR5V
+5V 90% 10%
tF5V
tR15V
+15V
tF15V tR15V
2.100
03759-A-019
-10V 90% 10% -3V
tR10V
0.875
0.200
0.250
tF10V
LOAD
03759-A-018
SOLDER MASK BOARD METALLIZATION
Figure 19. Suggested LFCSP 4 mm x 4mm 20 Lead Land Pattern
SCAN/BLANK EXTERNAL CLOCK
Figure 17. Power Sequence
Rev. A | Page 10 of 12
ADM8832 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 12 MAX 0.90 0.85 0.80 SEATING 0.50 PLANE BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
0.60 MAX
16 15 EXPOSED PAD
(BOTTOM VIEW)
20 1
2.25 2.10 SQ 1.95
6 5
11 10
0.25 MIN 0.30 0.23 0.18
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body (CP-20) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM8832ACP ADM8832ACP-REEL ADM8832ACP-REEL7 ADM8832ACPZ1 ADM8832ACPZ-REEL1 ADM8832ACPZ-REEL71 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Package Option CP-20 CP-20 CP-20 CP-20 CP-20 CP-20
1
Z = Pb-free part.
Rev. A | Page 11 of 12
ADM8832 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03759-0-5/04(A)
Rev. A | Page 12 of 12

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